This invention relates to circuits for multiplying two multibit binary numbers together.
Basically, two multibit binary numbers can be expressed mathematically as X.sub.n +. . .+X.sub.1 +X.sub.0 and Y.sub.n +. . .+Y.sub.1 +Y.sub.0. In this expression, X.sub.0 is the bit of power 0 in the number X; Y.sub.0 is the bit of power 0 in the number Y; X.sub.1 is the bit of power 1 in the number X; etc. And, to form the product of the two numbers X and Y, each bit in the number X must be multiplied by all of the bits in the number Y to thereby form a plurality of single power product terms. Then, all of the single power product terms must be added together.
One prior art multiplier circuit which forms and adds the single power product terms in a serial fashion, one term at a time, is described at page 340 of the textbook Principles of CMOS VLSI Design by N. West and K. Eshraghian, 1985, from Addison-Wesley. That reference, at page 345, also describes a faster prior art multiplier circuit which forms and adds the single power product terms by means of one large array of two-bit and three-bit adders. However, both of these multiplier circuits are still too slow for many applications-such as high speed real time signal processing.
Accordingly, a primary object of the invention is to provide a multiplier circuit which has a novel architecture whereby products are formed very quickly.